1. Field of the Invention
The present invention relates to digital circuits. In particular, the present invention relates to clock signal generation circuits.
2. Discussion of the Related Art
In a typical prior art clock signal generation circuit, the output circuit includes a frequency divider that has integer modulus steps (i.e., the output clock signal is derived from dividing the frequency of a source clock signal, such as an internal clock signal, by an integer). In other words, the output signal has a frequency which is an integer submultiple of the frequency of the source clock signal. In this context, an integer submultiple frequency refers to the frequency obtained by dividing a source frequency by an integer.
FIG. 1 is a block diagram of conventional clock generation circuit 100. As shown in FIG. 1, clock generation circuit 100 includes phase-locked loop (PLL) 101 and output frequency divider 102. PLL 1010 typically includes a voltage-controlled oscillator (VCO) that operates within a frequency range between fLO and fHI. The performance of PLL 101 is often limited by its VCO. This is because a VCO that operates at a high absolute operating frequency or that operates over a wide frequency range, generally has a lower performance and a greater complexity than VCOs that operate at lower frequencies or over a narrower range. In a clock signal generation circuit, such as clock generation circuit 100 of FIG. 1, its highest output frequency fmax is related to its VCO's highest operating frequency fHI by the equation:fHI=fmax×Nmin where Nmin is the least divider. Additionally, if clock signal generator 100 is required to provide an output frequency that is to be continuously programmable to a lower frequency without any significant coverage gap, the VCO frequency range must be wide enough to cover the ratio from Nmin, to the next lowest N value (i.e., Nmin+1), i.e.,
            f      HI              f      LO        ≥            N              min        +        1                    N      min      